
-------------Din Generator---------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Dinclk is
	port(	clk: in std_logic;
			reset			: in std_logic;
			iyin 		: in std_logic_vector(7 downto 0);
			idin		: in std_logic_vector (11 downto 0);
			id			: out std_logic;
			idr			: out std_logic;
			clkout		: out std_logic
			);
END Dinclk;

ARCHITECTURE beh of Dinclk is

	TYPE STATETYPE IS (S0, S1, S2, S3, S4, S5, S6);
	SIGNAL currstate, nextstate: statetype;
	constant Dcon : std_logic_vector(11 downto 0) := "100111111110";
	constant Dcon2 : std_logic_vector(11 downto 0) := "000000001000";
	constant Ycon : std_logic_vector(7 downto 0) := "11101111";
begin
state: PROCESS (currstate, reset, iyin, idin)
		BEGIN
			CASE currstate IS
				WHEN S0 =>
					clkout <= '0';
					
					id <= '0';
					idr <= '1';
					nextstate <= S5;
				WHEN S1 =>
					
					clkout <= '0';
					
					id <= '1';
					idr <= '0';
					if (idin = Dcon2) then
						nextstate <= S3;
					else
						nextstate <= S2;
					End if;
					
					
				WHEN S2 =>
					
					clkout <= '0';
					
					id <= '1';
					idr <= '0';
					
					if (idin = Dcon2) then
						nextstate <= S3;
					else
						nextstate <= S1;
					End if;
				
				WHEN S3 =>
					
					clkout <= '1';
					
					id <= '1';
					idr <= '0';
					
					if (idin = Dcon + Dcon2) then
						nextstate <= S5;
					else
						nextstate <= S4;
					End if;
					
					
				WHEN S4 =>
					
					clkout <= '1';
					
					id <= '1';
					idr <= '0';
					
					if (idin = Dcon + Dcon2) then
						nextstate <= S5;
					else
						nextstate <= S4;
					End if; 
					
				WHEN S5 =>
						
					clkout <= '0';
					
					id <= '0';
					idr <= '1';
					
					If (iyin = Ycon)then
						nextstate <= S1;
					else
						nextstate <= S6;
					End if;
					
				WHEN S6 =>
						
					clkout <= '0';
					
					id <= '0';
					idr <= '1';
					
					If (iyin = Ycon)then
						nextstate <= S1;
					else
						nextstate <= S5;
					End if;
					
				END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				IF (reset = '0') THEN
					currstate <= S0;
				ELSE
					currstate <= nextstate;
				END IF;
			END IF;
		END PROCESS statereg;
		
end beh;

----------XYclk-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity XYclk is
	 port(	clk			: in std_logic;
			reset			: in std_logic;
			ixin		: in std_logic_vector(7 downto 0);
			ix			: out std_logic;
			ixr			: out std_logic;
			iyin		: in std_logic_vector(7 downto 0);
			iy			: out std_logic;
			iyr			: out std_logic;
			clkout		: out std_logic_vector (1 downto 0)
			);
end XYclk;

architecture Behavioral of XYclk is

	TYPE STATETYPE IS (S0, S1, S2, S3, S3c, S3b, S4, S4b, S4c);
	SIGNAL currstate, nextstate: statetype;

	constant Ycon : std_logic_vector(7 downto 0) := "11101111";
	constant Xcon : std_logic_vector(7 downto 0) := "10011111";

	
begin
state: PROCESS (currstate, reset, ixin, iyin)
		BEGIN
			CASE currstate IS
				WHEN S0 =>
					clkout(1) <= '1';
					clkout(0) <= '1';
					iy <= '0';
					iyr <= '1';
					ix <= '0';
					ixr <= '1';
					nextstate <= S1;
				WHEN S1 =>
					clkout(1) <= '0';
					clkout(0) <= '0';
				
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					if (ixin = Xcon) then
						if (iyin = Ycon) then
							nextstate <= S4;
						else
							nextstate <= S3;
						end if;	
					
					else
						nextstate <= S2;
					end if;

				WHEN S2 =>	
					
					clkout(1) <= '0';
					clkout(0) <= '1';	
									
					iy <= '0';
					iyr <= '0';
					ix <= '1';
					ixr <= '0';

					nextstate <= S1;
									
				WHEN S3 =>
					
					clkout(1) <= '1';
					clkout(0) <= '1';	
					
					iy <= '1';
					iyr <= '0';
					ix <= '0';
					ixr <= '1';

					nextstate <= S3b;
					
				WHEN S3b =>
					
					clkout(1) <= '1';
					clkout(0) <= '0';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					nextstate <= S3c;
				
				WHEN S3c =>
					
					clkout(1) <= '0';
					clkout(0) <= '1';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '1';
					ixr <= '0';

					nextstate <= S1;
					
				WHEN S4 =>
				
					clkout(1) <= '1';
					clkout(0) <= '1';	
					
					iy <= '0';
					iyr <= '1';
					ix <= '0';
					ixr <= '1';

					nextstate <= S4b;

				WHEN S4b =>
					
					clkout(1) <= '1';
					clkout(0) <= '0';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					nextstate <= S4c;
				
				WHEN S4c =>
					
					clkout(1) <= '0';
					clkout(0) <= '1';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '1';
					ixr <= '0';

					nextstate <= S1;
				
			END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk, reset)
		BEGIN
			IF (reset = '0') THEN
				currstate <= S0;
			ELSE
				IF (clk = '1' and clk'event) THEN
					currstate <= nextstate;
				END IF;
			END IF;
		END PROCESS statereg;
					
			
end Behavioral;

-----------3bit d flipflop------------------

library ieee ;
use ieee.std_logic_1164.all;
use work.all;

entity My_dff is
	port(	clk			: in std_logic;
			data_in		: in std_logic_vector (2 downto 0);
			data_out	: out std_logic_vector (2 downto 0)
		);
end My_dff;

architecture behv of My_dff is
begin

process(data_in, clk)
	begin
		if (clk='1' and clk'event) then
			data_out <= data_in;
		end if;
	end process;
end behv;

-----------8 bit d flipflop------------------

library ieee ;
use ieee.std_logic_1164.all;
use work.all;

entity My_8bdff is
	port(	clk			: in std_logic;
			data_in		: in std_logic_vector (7 downto 0);
			data_out	: out std_logic_vector (7 downto 0)
		);
end My_8bdff;

architecture behv of My_8bdff is
begin

process(data_in, clk)
	begin
		if (clk='1' and clk'event) then
			data_out <= data_in;
		end if;
	end process;
end behv;

------8 Cycle Clock Divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity My_8clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			reset  		: in std_logic
			);
end My_8clkdiv;

architecture behavior of My_8clkdiv is
	constant num : integer := 8;
	signal cnt : integer := 0;
	begin
		process(clk, reset)
			begin
				if(clk'event and clk='1') then
					if (reset = '1') then
						if(cnt > (num/2 - 1))then
							clkout <= '0';
							cnt <= cnt+1;
							if(cnt = num-1)then
								cnt <= 0;
							end if;
						else
							cnt <= cnt+1;
							clkout <='1';
						end if;
					else
						clkout <= '0';
						cnt <= 0;
					end if;
				END if;
		end process;
end behavior;

------8 Cycle Clock Divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity My_8clkdiv2 is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			reset  		: in std_logic
			);
end My_8clkdiv2;

architecture behavior of My_8clkdiv2 is
	constant num : integer := 8;
	signal cnt : integer := 0;
	begin
		process(clk, reset)
			begin
				if(clk'event and clk='1') then
					if (reset = '1') then
						if(cnt = 0)then
							clkout <= '1';
							cnt <= cnt+1;
						else
							cnt <= cnt+1;
							clkout <= '0';
							if(cnt = num-1)then
								cnt <= 0;
							end if;
						end if;
					else
						clkout <= '0';
						cnt <= 0;
					end if;
				END if;
		end process;
end behavior;

------ 16 Cycle Clock Divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity My_16clkdiv2 is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			reset  		: in std_logic
			);
end My_16clkdiv2;

architecture behavior of My_16clkdiv2 is
	constant num : integer := 16;
	signal cnt : integer := 8;
	begin
		process(clk, reset)
			begin
				if(clk'event and clk='1') then
					if (reset = '1') then
						if(cnt = 0)then
							clkout <= '1';
							cnt <= cnt+1;
						else
							cnt <= cnt+1;
							clkout <= '0';
							if(cnt = num-1)then
								cnt <= 0;
							end if;
						end if;
					else
						clkout <= '0';
						cnt <= 8;
					end if;
				END if;
		end process;
end behavior;

------ 16 Cycle Clock Divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity My_16clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			reset  		: in std_logic
			);
end My_16clkdiv;

architecture behavior of My_16clkdiv is
	constant num : integer := 16;
	signal cnt : integer := 0;
	begin
		process(clk, reset)
			begin
				if(clk'event and clk='1') then
					if (reset = '1') then
						if(cnt > (num/2 - 9))then
							clkout <= '0';
							cnt <= cnt+1;
							if(cnt = num-9)then
								cnt <= -8;
							end if;
						else
							cnt <= cnt+1;
							clkout <='1';
						end if;
					else
						clkout <= '0';
						cnt <= 0;
					end if;
				END if;
		end process;
end behavior;

----------6bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_6bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (5 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_6bCounter;  

ARCHITECTURE behav OF My_6bCounter IS
	SIGNAL buff : std_logic_vector (5 downto 0) := "000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "000000";
			else
				if (count = '1') then
					buff <= buff + "000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

----------8bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_8bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (7 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_8bCounter;  

ARCHITECTURE behav OF My_8bCounter IS
	SIGNAL buff : std_logic_vector (7 downto 0) := "00000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "00000000";
			else
				if (count = '1') then
					buff <= buff + "00000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

----------9bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_9bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (8 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_9bCounter;  

ARCHITECTURE behav OF My_9bCounter IS
	SIGNAL buff : std_logic_vector (8 downto 0) := "000000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "000000000";
			else
				if (count = '1') then
					buff <= buff + "000000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

----------12bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_12bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (11 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_12bCounter;  

ARCHITECTURE behav OF My_12bCounter IS
	SIGNAL buff : std_logic_vector (11 downto 0) := "000000000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "000000000000";
			else
				if (count = '1') then
					buff <= buff + "000000000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

----------16bit index ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_16index IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (15 downto 0);
			counterR	: OUT std_logic_vector (15 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_16index;  

ARCHITECTURE behav OF My_16index IS
	SIGNAL buff : std_logic_vector (15 downto 0) := "0000000000000001";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "0000000000000001";
			else
				if (count = '1') then
					buff <= buff(14 downto 0)&buff(15);
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
	counterR <= not buff;
END behav;

---------- 18bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_18bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_18bCounter;  

ARCHITECTURE behav OF My_18bCounter IS
	SIGNAL buff : std_logic_vector (17 downto 0) := (OTHERS => '0');
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= (OTHERS => '0');
			else
				if (count = '1') then
					buff <= buff + "000000000000000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

---------- 18bit Counter40_0 ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_18bCounter40_0 IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_18bCounter40_0;  

ARCHITECTURE behav OF My_18bCounter40_0 IS
	SIGNAL buff : std_logic_vector (17 downto 0) := "000000000000000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "000000000000000000";
			else
				if (count = '1') then
					buff <= buff + "000000000000101000";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

---------- 18bit Counter40 ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_18bCounter40 IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_18bCounter40;  

ARCHITECTURE behav OF My_18bCounter40 IS
	SIGNAL buff : std_logic_vector (17 downto 0) := "000001001001101010";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "000001001001101010";
			else
				if (count = '1') then
					buff <= buff + "000000000000101000";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

----------Print Screen----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity My_printsceern is
	port(
			clk		: in std_logic;
			reset	: in STD_logic;
			data_inU: in STD_logic_vector (15 downto 0);
			data_inL: in STD_logic_vector (15 downto 0);
			GPIO_0	: inout STD_logic_vector (7 downto 0)
		);
end My_printsceern;

architecture beh of My_printsceern is
SIGNAL count : integer := 0;
begin
state: PROCESS (clk, reset, data_inU, data_inL)
BEGIN
	If (clk = '1' and clk'event) then
		if (reset = '0') then
			count <= 0;
			GPIO_0 (7 downto 0) <= (OTHERS => '1');
		else
			if (count < 8) then
				count <= count + 1;
				GPIO_0 (7 downto 0) <= (OTHERS => '1');
			else
				if (count < 24) then
					count <= count + 1;
					GPIO_0 (3 downto 0) <= data_inU (3 downto 0);
					GPIO_0 (7 downto 4) <= data_inL (3 downto 0);
				else
					if (count < 40) then
						count <= count + 1;
						GPIO_0 (3 downto 0) <= data_inU (7 downto 4);
						GPIO_0 (7 downto 4) <= data_inL (7 downto 4);
					else
						if (count < 56) then
							count <= count + 1;
							GPIO_0 (3 downto 0) <= data_inU (11 downto 8);
							GPIO_0 (7 downto 4) <= data_inL (11 downto 8);
						else
							if (count < 71) then
								count <= count + 1;
								GPIO_0 (3 downto 0) <= data_inU (15 downto 12);
								GPIO_0 (7 downto 4) <= data_inL (15 downto 12);
							else
								count <= 8;
								GPIO_0 (3 downto 0) <= data_inU (15 downto 12);
								GPIO_0 (7 downto 4) <= data_inL (15 downto 12);
							end if;
						end if;
					end if;
				end if;
			end if;
		end if;
	end if;
END PROCESS state;
end beh;

--architecture beh of My_printsceern is
--
--	TYPE STATETYPE IS (S0, S1, S2, S3, S4);
--	SIGNAL currstate, nextstate: statetype;
--	constant Ycon : std_logic_vector(7 downto 0) := "11101111";
--	
--begin
--state: PROCESS (currstate, reset, data_inU, data_inL)
--		BEGIN
--			CASE currstate IS
--				
--				WHEN S0 =>
--					GPIO_0 (3 downto 0) <= data_inU (3 downto 0);
--					GPIO_0 (7 downto 4) <= data_inL (3 downto 0);
--					nextstate <= S1;
--					
--				WHEN S1 =>
--					GPIO_0 (3 downto 0) <= data_inU (3 downto 0);
--					GPIO_0 (7 downto 4) <= data_inL (3 downto 0);
--					nextstate <= S2;
--					
--				WHEN S2 =>
--				
--					GPIO_0 (3 downto 0) <= data_inU (7 downto 4);
--					GPIO_0 (7 downto 4) <= data_inL (7 downto 4);
--					nextstate <= S3;
--					
--				WHEN S3 =>
--				
--					GPIO_0 (3 downto 0) <= data_inU (11 downto 8);
--					GPIO_0 (7 downto 4) <= data_inL (11 downto 8);
--					nextstate <= S4;
--					
--				WHEN S4 =>
--				
--					GPIO_0 (3 downto 0) <= data_inU (15 downto 12);
--					GPIO_0 (7 downto 4) <= data_inL (15 downto 12);
--					nextstate <= S1;
--					
--				END CASE;
--		END PROCESS state;
--		Statereg: PROCESS (clk, reset)
--		BEGIN
--			IF (reset = '0') THEN
--				currstate <= S0;
--			ELSE
--				IF (clk = '1' and clk'event) THEN
--					currstate <= nextstate;
--				END IF;
--			END IF;
--		END PROCESS statereg;
--end beh;

------------sram control----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity My_sramctrl is
	port(
			clk			: in std_logic;
			reset		: in STD_logic;
			dinin		: in STD_logic_vector (11 downto 0);
			
			SRAM_ADDR 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
			SRAM_WE_N 	: OUT STD_LOGIC;
			SRAM_OE_N 	: OUT STD_LOGIC;
			SRAM_CE_N 	: OUT STD_LOGIC;
			SRAM_UB_N 	: OUT STD_LOGIC;
			SRAM_LB_N 	: OUT STD_LOGIC;
			SRAM_DQ 	: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			
			adcounter	: in std_logic_vector (17 downto 0);
			adcount 	: out std_logic;
			adreset		: out std_logic;
			
			dlycounter	: in std_logic_vector (5 downto 0);
			dlycount 	: out std_logic;
			dlyreset	: out std_logic;
			
			frmcounter	: in std_logic_vector (17 downto 0);
			frmcount 	: out std_logic;
			frmreset	: out std_logic;
			
			numcounter	: in std_logic_vector (17 downto 0);
			numcount	: out std_logic;
			numreset	: out std_logic;
			
			saocounter	: in std_logic_vector (17 downto 0);
			saocount	: out std_logic;
			saoreset	: out std_logic;
			
			graphcounter	: in std_logic_vector (17 downto 0);
			graphcount	: out std_logic;
			graphreset	: out std_logic;
			
			fillcounter	: in std_logic_vector (17 downto 0);
			fillcount	: out std_logic;
			fillreset	: out std_logic;
			
			indxcounter	: in std_logic_vector (15 downto 0);
			indxcounterR: in std_logic_vector (15 downto 0);
			indxcount	: out std_logic;
			indxreset	: out std_logic;
			
			Ur_reset 	: OUT std_logic;
			Ur_load 	: OUT std_logic;
			Ur_data_in	: OUT std_logic_vector (15 downto 0);
			Lr_reset 	: OUT std_logic;
			Lr_load 	: OUT std_logic;
			Lr_data_in	: OUT std_logic_vector (15 downto 0);
			
			numr_reset 	: OUT std_logic;
			numr_load 	: OUT std_logic;
			numr_data_in: OUT std_logic_vector (15 downto 0);
			numr_data_out: IN std_logic_vector (15 downto 0);
			
			delr_reset 	: OUT std_logic;
			delr_load 	: OUT std_logic;
			delr_data_in: OUT std_logic_vector (15 downto 0);
			delr_data_out: IN std_logic_vector (15 downto 0);
			
			adr_reset 	: OUT std_logic;
			adr_load 	: OUT std_logic;
			adr_data_in: OUT std_logic_vector (17 downto 0);
			adr_data_out: IN std_logic_vector (17 downto 0);
			adr_data_out2: IN std_logic_vector (17 downto 0);
			adr_data_out3: IN std_logic_vector (17 downto 0);
			
			data_in1	: in std_logic_vector (7 downto 0);
			data_in2	: in std_logic_vector (7 downto 0);
			data_in3	: in std_logic_vector (7 downto 0);
			data_in4	: in std_logic_vector (7 downto 0);
			data_frame	: in std_logic;
			data_sao	: in std_logic;
			data_bpm	: in std_logic;
			data_graph	: in std_logic;
			data_ready	: in std_logic;
			data_stored	: out std_logic;
			
			flag_reset: OUT std_logic;
			flag_on	: OUT std_logic;
			flag_in	: IN std_logic
			);
end My_sramctrl;

architecture beh of My_sramctrl is

	TYPE STATETYPE IS (S0U, S0L, S1U, S1L, S_init_delay1, S_init_delay2, S_init_delay3, S_init_delay4, S_init_delay5, S_init_delay6, S_init_delay7,
	S_loop_delay1, S_loop_delay2
	, S_store_frame1, S_store_frame2
	, S_store_sao1, S_store_sao2, S_store_sao3, S_store_sao4, S_store_sao5, S_store_sao6
	, S_store_bpm1, S_store_bpm2, S_store_bpm3, S_store_bpm4, S_store_bpm5, S_store_bpm6
	, S_store_graph1_erase, S_store_graph2_erase, S_store_graph1_write, S_store_graph2_write, S_store_graph1
	);
	SIGNAL currstate, nextstate: statetype;
	constant fiftynine : std_logic_vector(5 downto 0) := "111011";
	constant fiftyseven : std_logic_vector(5 downto 0) := "111001";
	constant three : std_logic_vector(5 downto 0) := "000011";
	constant thirty : std_logic_vector(5 downto 0) := "011110";
	constant sixty : std_logic_vector(5 downto 0) := "111100";
	constant sixtyone : std_logic_vector(5 downto 0) := "111101";
	constant zeroz : std_logic_vector(5 downto 0) := "000000";
	constant dincon : std_logic_vector(11 downto 0) := "000000000100";
	constant highz : std_logic_vector(15 downto 0) := "ZZZZZZZZZZZZZZZZ";
	constant ad_zero : std_logic_vector(17 downto 0) := "000000000000000001";
	constant ad_one : std_logic_vector(17 downto 0) := "000000000000000001";
	constant ad_three : std_logic_vector(17 downto 0) := "000000000000000011";
	constant ad_thirtyeight : std_logic_vector(17 downto 0) := "000000000000100110";
	constant ad_middle : std_logic_vector(17 downto 0) := "000010010110000000";
	constant ad_numbers : std_logic_vector(17 downto 0) := "000100101100000000";
	constant fifteen : std_logic_vector(8 downto 0) := "000001111";
	constant fourty : std_logic_vector(8 downto 0) := "000101000";
	constant ad_fourseventy : std_logic_vector(17 downto 0) := "000100100101110000";
	constant thirtynine : std_logic_vector(17 downto 0) := "000000000000100111";
	
begin
state: PROCESS (currstate, reset, dinin, SRAM_DQ, adcounter, dlycounter, frmcounter, numcounter, saocounter, graphcounter, fillcounter, indxcounter, indxcounterR,
				numr_data_out, delr_data_out, adr_data_out, adr_data_out2, adr_data_out3, flag_in,
				data_in1, data_in2, data_in3, data_in4, data_frame,
				data_sao, data_bpm, data_graph, data_ready
				)
		BEGIN
			CASE currstate IS
				WHEN S_init_delay1 =>
					fillcount <= '0'; fillreset <= '1'; indxcount <= '0'; indxreset <= '1'; graphcount <= '0'; graphreset <= '1'; adR_data_in <= (OTHERS => '0'); adR_load <= '0'; adR_reset <= '1'; delR_data_in <= (OTHERS => '0'); delR_load <= '0'; delR_reset <= '1'; flag_on <= '0'; flag_reset <= '1'; numr_data_in <= (OTHERS => '0'); numr_load <= '0'; numr_reset <= '1'; numcount <= '0'; numreset <= '0'; saocount <= '0'; saoreset <= '0'; Ur_data_in <= SRAM_DQ; Lr_data_in <= SRAM_DQ; SRAM_DQ <= highz; SRAM_ADDR <= ad_middle; SRAM_WE_N <= '1'; SRAM_OE_N <= '1'; SRAM_CE_N <= '0'; SRAM_UB_N <= '1'; SRAM_LB_N <= '1'; adcount <= '0'; adreset <= '1'; Ur_reset <= '1'; Ur_load <= '0'; Lr_reset <= '1'; Lr_load <= '0'; dlycount <= '0'; dlyreset <= '1'; frmcount <= '0'; frmreset <= '1'; data_stored <= '0'; nextstate <= S_init_delay2;
				WHEN S_init_delay2 =>
					fillcount <= '0'; fillreset <= '0'; indxcount <= '0'; indxreset <= '0'; graphcount <= '0'; graphreset <= '0'; adR_data_in <= (OTHERS => '0'); adR_load <= '0'; adR_reset <= '0'; delR_data_in <= (OTHERS => '0'); delR_load <= '0'; delR_reset <= '0'; flag_on <= '0'; flag_reset <= '1'; numr_data_in <= (OTHERS => '0'); numr_load <= '0'; numr_reset <= '1'; numcount <= '0'; numreset <= '0'; saocount <= '0'; saoreset <= '0'; Ur_data_in <= SRAM_DQ; Lr_data_in <= SRAM_DQ; SRAM_DQ <= highz; SRAM_ADDR <= ad_middle; SRAM_WE_N <= '1'; SRAM_OE_N <= '1'; SRAM_CE_N <= '0'; SRAM_UB_N <= '1'; SRAM_LB_N <= '1'; adcount <= '0'; adreset <= '1'; Ur_reset <= '1'; Ur_load <= '0'; Lr_reset <= '1'; Lr_load <= '0'; dlycount <= '0'; dlyreset <= '1'; frmcount <= '0'; frmreset <= '1'; data_stored <= '0'; nextstate <= S_init_delay3;
				WHEN S_init_delay3 =>
					fillcount <= '0'; fillreset <= '0'; indxcount <= '0'; indxreset <= '0'; graphcount <= '0'; graphreset <= '0'; adR_data_in <= (OTHERS => '0'); adR_load <= '0'; adR_reset <= '0'; delR_data_in <= (OTHERS => '0'); delR_load <= '0'; delR_reset <= '0'; flag_on <= '0'; flag_reset <= '1'; numr_data_in <= (OTHERS => '0'); numr_load <= '0'; numr_reset <= '1'; numcount <= '0'; numreset <= '0'; saocount <= '0'; saoreset <= '0'; Ur_data_in <= SRAM_DQ; Lr_data_in <= SRAM_DQ; SRAM_DQ <= highz; SRAM_ADDR <= ad_middle; SRAM_WE_N <= '1'; SRAM_OE_N <= '1'; SRAM_CE_N <= '0'; SRAM_UB_N <= '1'; SRAM_LB_N <= '1'; adcount <= '0'; adreset <= '1'; Ur_reset <= '1'; Ur_load <= '0'; Lr_reset <= '1'; Lr_load <= '0'; dlycount <= '0'; dlyreset <= '1'; frmcount <= '0'; frmreset <= '1'; data_stored <= '0'; nextstate <= S_init_delay4;
				WHEN S_init_delay4 =>
					fillcount <= '0'; fillreset <= '0'; indxcount <= '0'; indxreset <= '0'; graphcount <= '0'; graphreset <= '0'; adR_data_in <= (OTHERS => '0'); adR_load <= '0'; adR_reset <= '0'; delR_data_in <= (OTHERS => '0'); delR_load <= '0'; delR_reset <= '0'; flag_on <= '0'; flag_reset <= '1'; numr_data_in <= (OTHERS => '0'); numr_load <= '0'; numr_reset <= '1'; numcount <= '0'; numreset <= '0'; saocount <= '0'; saoreset <= '0'; Ur_data_in <= SRAM_DQ; Lr_data_in <= SRAM_DQ; SRAM_DQ <= highz; SRAM_ADDR <= ad_middle; SRAM_WE_N <= '1'; SRAM_OE_N <= '1'; SRAM_CE_N <= '0'; SRAM_UB_N <= '1'; SRAM_LB_N <= '1'; adcount <= '0'; adreset <= '1'; Ur_reset <= '1'; Ur_load <= '0'; Lr_reset <= '1'; Lr_load <= '0'; dlycount <= '0'; dlyreset <= '1'; frmcount <= '0'; frmreset <= '1'; data_stored <= '0'; nextstate <= S_init_delay5;
				WHEN S_init_delay5 =>
					fillcount <= '0'; fillreset <= '0'; indxcount <= '0'; indxreset <= '0'; graphcount <= '0'; graphreset <= '0'; adR_data_in <= (OTHERS => '0'); adR_load <= '0'; adR_reset <= '0'; delR_data_in <= (OTHERS => '0'); delR_load <= '0'; delR_reset <= '0'; flag_on <= '0'; flag_reset <= '1'; numr_data_in <= (OTHERS => '0'); numr_load <= '0'; numr_reset <= '1'; numcount <= '0'; numreset <= '0'; saocount <= '0'; saoreset <= '0'; Ur_data_in <= SRAM_DQ; Lr_data_in <= SRAM_DQ; SRAM_DQ <= highz; SRAM_ADDR <= ad_middle; SRAM_WE_N <= '1'; SRAM_OE_N <= '1'; SRAM_CE_N <= '0'; SRAM_UB_N <= '1'; SRAM_LB_N <= '1'; adcount <= '0'; adreset <= '1'; Ur_reset <= '1'; Ur_load <= '0'; Lr_reset <= '1'; Lr_load <= '0'; dlycount <= '0'; dlyreset <= '1'; frmcount <= '0'; frmreset <= '1'; data_stored <= '0'; nextstate <= S_init_delay6;
				WHEN S_init_delay6 =>
					fillcount <= '0'; fillreset <= '0'; indxcount <= '0'; indxreset <= '0'; graphcount <= '0'; graphreset <= '0'; adR_data_in <= (OTHERS => '0'); adR_load <= '0'; adR_reset <= '0'; delR_data_in <= (OTHERS => '0'); delR_load <= '0'; delR_reset <= '0'; flag_on <= '0'; flag_reset <= '1'; numr_data_in <= (OTHERS => '0'); numr_load <= '0'; numr_reset <= '1'; numcount <= '0'; numreset <= '0'; saocount <= '0'; saoreset <= '0'; Ur_data_in <= SRAM_DQ; Lr_data_in <= SRAM_DQ; SRAM_DQ <= highz; SRAM_ADDR <= ad_middle; SRAM_WE_N <= '1'; SRAM_OE_N <= '1'; SRAM_CE_N <= '0'; SRAM_UB_N <= '1'; SRAM_LB_N <= '1'; adcount <= '0'; adreset <= '1'; Ur_reset <= '1'; Ur_load <= '0'; Lr_reset <= '1'; Lr_load <= '0'; dlycount <= '0'; dlyreset <= '1'; frmcount <= '0'; frmreset <= '1'; data_stored <= '0'; nextstate <= S_init_delay7;
				WHEN S_init_delay7 =>
					fillcount <= '0'; fillreset <= '0'; indxcount <= '0'; indxreset <= '0'; graphcount <= '0'; graphreset <= '0'; adR_data_in <= (OTHERS => '0'); adR_load <= '0'; adR_reset <= '0'; delR_data_in <= (OTHERS => '0'); delR_load <= '0'; delR_reset <= '0'; flag_on <= '0'; flag_reset <= '1'; numr_data_in <= (OTHERS => '0'); numr_load <= '0'; numr_reset <= '1'; numcount <= '0'; numreset <= '1'; saocount <= '0'; saoreset <= '1'; Ur_data_in <= SRAM_DQ; Lr_data_in <= SRAM_DQ; SRAM_DQ <= highz; SRAM_ADDR <= ad_middle; SRAM_WE_N <= '1'; SRAM_OE_N <= '1'; SRAM_CE_N <= '0'; SRAM_UB_N <= '1'; SRAM_LB_N <= '1'; adcount <= '0'; adreset <= '1'; Ur_reset <= '1'; Ur_load <= '0'; Lr_reset <= '1'; Lr_load <= '0'; dlycount <= '0'; dlyreset <= '1'; frmcount <= '0'; frmreset <= '1'; data_stored <= '0'; nextstate <= S0U;
					
				WHEN S0U =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_zero;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '0';
					adreset <= '1';
					dlycount <= '0';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '1';
					Lr_reset <= '0';
					Lr_load <= '0';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S0L;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S0L =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_middle;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '1';
					adreset <= '0';
					dlycount <= '0';
					dlyreset <= '1';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '1';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S_loop_delay1;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_loop_delay1 =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_DQ <= highz;
					SRAM_ADDR <= ad_middle;
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '1';
					SRAM_LB_N <= '1';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					
					if (dlycounter = zeroz and data_ready = '1') then
						if (data_graph = '1') then
							if (flag_in = '0') then
								nextstate <= S_store_graph1_erase;
							else
								nextstate <= S_store_graph1_write;
							end if;
						else
							if (data_frame = '1') then
								nextstate <= S_store_frame1;
							else
								if (data_bpm = '1') then
									if (flag_in = '0') then
										nextstate <= S_store_bpm1;
									else
										nextstate <= S_store_bpm5;
									end if;
								else
									if (flag_in = '0') then
										nextstate <= S_store_sao1;
									else
										nextstate <= S_store_sao5;
									end if;
								end if;
							end if;
						end if;
					else
						if (dlycounter = sixtyone) then
							if (dinin = dincon) then
								nextstate <= S0U;
							else
								nextstate <= S1U;
							end if;
						else
							nextstate <= S_loop_delay2;
						end if;
					End if;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_loop_delay2 =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_DQ <= highz;
					SRAM_ADDR <= ad_middle;
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '1';
					SRAM_LB_N <= '1';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					if (dlycounter = sixtyone) then
						if (dinin = dincon) then
							nextstate <= S0U;
						else
							nextstate <= S1U;
						end if;
					else
						nextstate <= S_loop_delay1;
					end if;
					
					indxcount <= '0';
					indxreset <= '0';
					
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S1U =>
				
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= adcounter;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '0';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '1';
					Lr_reset <= '0';
					Lr_load <= '0';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S1L;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S1L =>
				
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= adcounter + ad_middle;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '1';
					adreset <= '0';
					dlycount <= '0';
					dlyreset <= '1';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '1';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S_loop_delay1;
				
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_frame1 =>
				
					SRAM_DQ <= data_in2&data_in1;
	
					SRAM_ADDR <= frmcounter;
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '1';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S_store_frame2;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_frame2 =>
					
					SRAM_DQ <= data_in4&data_in3;
	
					SRAM_ADDR <= frmcounter;
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '1';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '1';
					nextstate <= S_loop_delay2;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_sao1 =>
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_numbers + numcounter + (("0"&data_in1)*fifteen);
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= SRAM_DQ;
					numr_load <= '1';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '1';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S_store_sao2;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_sao2 =>
					SRAM_DQ <= numr_data_out;
					
					SRAM_ADDR <= saocounter;
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					if (dlycounter = thirty) then
						numcount <= '0';
						numreset <= '1';
						saocount <= '0';
						saoreset <= '1';
						nextstate <= S_store_sao3;
					else
						numcount <= '0';
						numreset <= '0';
						saocount <= '1';
						saoreset <= '0';
						nextstate <= S_store_sao1;
					end if;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_sao3 =>
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_numbers + numcounter + (("0"&data_in2)*fifteen);
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= SRAM_DQ;
					numr_load <= '1';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '1';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S_store_sao4;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_sao4 =>
					SRAM_DQ <= numr_data_out;
					
					SRAM_ADDR <= saocounter+ad_one;
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					data_stored <= '0';
					if (dlycounter = sixty) then
						numcount <= '0';
						numreset <= '1';
						saocount <= '0';
						saoreset <= '1';
						flag_on <= '1';
						flag_reset <= '0'; 
						nextstate <= S_loop_delay2;
					else
						numcount <= '0';
						numreset <= '0';
						saocount <= '1';
						saoreset <= '0';
						flag_on <= '0';
						flag_reset <= '0'; 
						nextstate <= S_store_sao3;
					end if;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_sao5 =>
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_numbers + numcounter + (("0"&data_in3)*fifteen);
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= SRAM_DQ;
					numr_load <= '1';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '1';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '1'; 
					data_stored <= '0';
					nextstate <= S_store_sao6;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_sao6 =>
					SRAM_DQ <= numr_data_out;
					
					SRAM_ADDR <= saocounter+ad_three;
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					if (dlycounter = thirty) then
						data_stored <= '1';
						numcount <= '0';
						numreset <= '1';
						saocount <= '0';
						saoreset <= '1';
						nextstate <= S_loop_delay2;
					else
						data_stored <= '0';
						numcount <= '0';
						numreset <= '0';
						saocount <= '1';
						saoreset <= '0';
						nextstate <= S_store_sao5;
					end if;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_bpm1 =>
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_numbers + numcounter + (("0"&data_in1)*fifteen);
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= SRAM_DQ;
					numr_load <= '1';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '1';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S_store_bpm2;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_bpm2 =>
					SRAM_DQ <= numr_data_out;
					
					SRAM_ADDR <= saocounter + "000000100101100000";
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					if (dlycounter = thirty) then
						numcount <= '0';
						numreset <= '1';
						saocount <= '0';
						saoreset <= '1';
						nextstate <= S_store_bpm3;
					else
						numcount <= '0';
						numreset <= '0';
						saocount <= '1';
						saoreset <= '0';
						nextstate <= S_store_bpm1;
					end if;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_bpm3 =>
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_numbers + numcounter + (("0"&data_in2)*fifteen);
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= SRAM_DQ;
					numr_load <= '1';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '1';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					nextstate <= S_store_bpm4;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_bpm4 =>
					SRAM_DQ <= numr_data_out;
					
					SRAM_ADDR <= saocounter+ "000000100101100001";
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					data_stored <= '0';
					if (dlycounter = sixty) then
						numcount <= '0';
						numreset <= '1';
						saocount <= '0';
						saoreset <= '1';
						flag_on <= '1';
						flag_reset <= '0'; 
						nextstate <= S_loop_delay2;
					else
						numcount <= '0';
						numreset <= '0';
						saocount <= '1';
						saoreset <= '0';
						flag_on <= '0';
						flag_reset <= '0'; 
						nextstate <= S_store_bpm3;
					end if;
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_bpm5 =>
					SRAM_DQ <= highz;
					
					SRAM_ADDR <= ad_numbers + numcounter + (("0"&data_in3)*fifteen);
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= SRAM_DQ;
					numr_load <= '1';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '1';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '1'; 
					data_stored <= '0';
					nextstate <= S_store_bpm6;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_bpm6 =>
					SRAM_DQ <= numr_data_out;
					
					SRAM_ADDR <= saocounter+"000000100101100010";
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					if (dlycounter = thirty) then
						data_stored <= '1';
						numcount <= '0';
						numreset <= '1';
						saocount <= '0';
						saoreset <= '1';
						nextstate <= S_loop_delay2;
					else
						data_stored <= '0';
						numcount <= '0';
						numreset <= '0';
						saocount <= '1';
						saoreset <= '0';
						nextstate <= S_store_bpm5;
					end if;
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
				WHEN S_store_graph1_erase =>
					SRAM_DQ <= highz;
					
					if (adR_data_out2 < adR_data_out3) then
						SRAM_ADDR <= adR_data_out2 + graphcounter + fillcounter;
					else
						SRAM_ADDR <= adR_data_out2 + graphcounter - fillcounter;
					end if;
					
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					
					delR_data_in <= SRAM_DQ;
					delR_load <= '1';
					delR_reset <= '0';
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					flag_on <= '0';
					flag_reset <= '0'; 
					nextstate <= S_store_graph2_erase;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					data_stored <= '0';
					flag_on <= '0';
					flag_reset <= '0'; 
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					
				WHEN S_store_graph2_erase =>
					SRAM_DQ <= indxcounter or delR_data_out;
					
					if (adR_data_out2 < adR_data_out3) then
						SRAM_ADDR <= adR_data_out2 + graphcounter + fillcounter;
						if (dlycounter = sixty) then
							nextstate <= S_loop_delay2;
							fillreset <= '0';
							fillcount <= '0';
						else
							if (adR_data_out2 + fillcounter = adR_data_out3) then
								nextstate <= S_store_graph1_write;
								fillreset <= '1';
								fillcount <= '0';
							else
								nextstate <= S_store_graph1_erase;
								fillreset <= '0';
								fillcount <= '1';
							end if;
						end if;
					else
						SRAM_ADDR <= adR_data_out2 + graphcounter - fillcounter;
						if (dlycounter = sixty) then 
							nextstate <= S_loop_delay2;
							fillreset <= '0';
							fillcount <= '1';
						else
							if (adR_data_out2 - fillcounter = adR_data_out3) then
								nextstate <= S_store_graph1_write;
								fillreset <= '1';
								fillcount <= '0';
							else
								nextstate <= S_store_graph1_erase;
								fillreset <= '0';
								fillcount <= '1';
							end if;
						end if;
					end if;
					
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					
				WHEN S_store_graph1_write =>
					SRAM_DQ <= highz;
					
					if (adR_data_out < ad_fourseventy - (("0"&data_in1)*fourty)) then
						SRAM_ADDR <= adR_data_out + graphcounter + fillcounter;
					else
						SRAM_ADDR <= adR_data_out + graphcounter - fillcounter;
					end if;
					
					adR_data_in <= (OTHERS => '0');
					adR_load <= '0';
					adR_reset <= '0';
					
					delR_data_in <= SRAM_DQ;
					delR_load <= '1';
					delR_reset <= '0';
					
					indxcount <= '0';
					indxreset <= '0';
					graphcount <= '0';
					graphreset <= '0';
					fillcount <= '0';
					fillreset <= '0';
					
					nextstate <= S_store_graph2_write;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					
					flag_on <= '0';
					flag_reset <= '0'; 
					data_stored <= '0';
					
					
				WHEN S_store_graph2_write =>
					SRAM_DQ <= delR_data_out and indxcounterR;
					
					if (adR_data_out < ad_fourseventy - (("0"&data_in1)*fourty)) then
						SRAM_ADDR <= adR_data_out + graphcounter + fillcounter;
						
						if (dlycounter = sixty) then
							nextstate <= S_loop_delay2;
							fillcount <= '1';
							flag_on <= '1';
						else
							if ((adR_data_out + fillcounter) = (ad_fourseventy - (("0"&data_in1)*fourty))) then
								nextstate <= S_store_graph1;
								fillcount <= '0';
								flag_on <= '0';
								
							else
								nextstate <= S_store_graph1_write;
								fillcount <= '1';
								flag_on <= '0';
							end if;
						end if;
					else
						SRAM_ADDR <= adR_data_out + graphcounter - fillcounter;
						if (dlycounter = sixty) then 
							nextstate <= S_loop_delay2;
							fillcount <= '0';
							flag_on <= '1';
						else
							if ((adR_data_out - fillcounter) = (ad_fourseventy - (("0"&data_in1)*fourty))) then
								nextstate <= S_store_graph1;
								fillcount <= '0';
								flag_on <= '0';
							else
								nextstate <= S_store_graph1_write;
								fillcount <= '1';
								flag_on <= '0';
							end if;
						end if;
					end if;
					
					data_stored <= '0';
					fillreset <= '0';
					indxcount <= '0';
					adR_load <= '0';
					graphcount <= '0';
					graphreset <= '0';
					flag_reset <= '0';
					adR_data_in <= ad_fourseventy - (("0"&data_in1)*fourty);
					
					adR_reset <= '0';
					indxreset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
					SRAM_WE_N <= '0';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
					
				WHEN S_store_graph1 =>

					SRAM_DQ <= (OTHERS => '0');
					SRAM_ADDR <= (OTHERS => '0');
					data_stored <= '1';
					fillcount <= '0';
					fillreset <= '1';
					indxcount <= '1';
					adR_load <= '1';
					
					if (indxcounter = "1000000000000000") then
						if (graphcounter = thirtynine) then
							graphcount <= '0';
							graphreset <= '1';
						else
							graphcount <= '1';
							graphreset <= '0';
						end if;
					else
						graphcount <= '0';
						graphreset <= '0';
					end if;
					
					nextstate <= S_loop_delay1;
					
					flag_on <= '0';
					flag_reset <= '1';
					adR_data_in <= ad_fourseventy - (("0"&data_in1)*fourty);
					
					adR_reset <= '0';
					indxreset <= '0';
					delR_data_in <= (OTHERS => '0');
					delR_load <= '0';
					delR_reset <= '0';
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '1';
					SRAM_LB_N <= '1';
					
					Ur_data_in <= (OTHERS => '0');
					Lr_data_in <= (OTHERS => '0');
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					numr_data_in <= (OTHERS => '0');
					numr_load <= '0';
					numr_reset <= '0';
					
					adcount <= '0';
					adreset <= '0';
					dlycount <= '1';
					dlyreset <= '0';
					frmcount <= '0';
					frmreset <= '0';
					numcount <= '0';
					numreset <= '0';
					saocount <= '0';
					saoreset <= '0';
				END CASE;
		END PROCESS state;
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				IF (reset = '0') THEN
					currstate <= S_init_delay1;
				ELSE
					currstate <= nextstate;
				END IF;
			END IF;
		END PROCESS statereg;
end beh;

---------- 16 Bit Register ----------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity My_16bRegister is

	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector (15 downto 0);
			data_out	: OUT std_logic_vector (15 downto 0)
			);
end My_16bRegister;

ARCHITECTURE behav OF My_16bRegister IS
BEGIN
PROCESS(clk, reset, load, data_in) 
	BEGIN
		if (clk'event and clk='1' and load = '1') then
			if (reset = '1') then
				data_out <= (OTHERS => '0');
			else
				data_out <= data_in;
			end if;
		end if;
	END PROCESS;
END behav;

---------- Address Register ----------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity My_addRegister is

	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector (17 downto 0);
			data_out	: OUT std_logic_vector (17 downto 0);
			data_out2	: OUT std_logic_vector (17 downto 0);
			data_out3	: OUT std_logic_vector (17 downto 0)
			);
end My_addRegister;

ARCHITECTURE behav OF My_addRegister IS
type address is array (640 downto 0) of std_logic_vector (17 downto 0);
signal addresses : address;
BEGIN
PROCESS(clk, reset, load, data_in, addresses) 
	BEGIN
		if (clk'event and clk='1' and load = '1') then
			if (reset = '1') then
				data_out <= (OTHERS => '0');
				addresses <= (0 => "000100100101110000", OTHERS=>(OTHERS => '0'));
			else
				addresses <= addresses (639 downto 0) & data_in;
			end if;
		end if;
		data_out <= addresses (0);
		data_out2 <= addresses (640);
		data_out3 <= addresses (639);
	END PROCESS;
END behav;

---------- flag ----------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity My_flag is

	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			flag_out	: OUT std_logic
			);
end My_flag;

ARCHITECTURE behav OF My_flag IS
BEGIN
PROCESS(clk, reset, load) 
	BEGIN
		if (clk'event and clk='1') then
			if (reset = '1') then
				flag_out <= '0';
			else
				if (load = '1') then
					flag_out <= '1';
				end if;
			end if;
		end if;
   END PROCESS;
END behav;

--------------UART ------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity uart is
	port(	clk			: in std_logic;
			reset		: in std_logic;
			rx_data		: out std_logic_vector (7 downto 0);
			rx_in		: in std_logic;
			rx_load		: out std_logic;

			tx_data		: in std_logic_vector (7 downto 0);
			tx_out		: out  std_logic;
			tx_send		: in std_logic
			);
end uart;
architecture rtl of uart is
	signal rx_count, rx_delay, tx_count, tx_delay: integer;
	signal rx_reading, tx_sending, rx_loading : std_logic;
	signal rx_prl_data, tx_prl_data: std_logic_vector (7 downto 0);
begin
-- read process---
	process (clk, reset)
	
		begin
	if (clk = '1' and clk'event) then
		if (reset = '0') then
			rx_prl_data <= "00000000";
			rx_delay <= 0;
			rx_count <= 0;
			rx_reading <= '0';
			rx_load <= '0';
			rx_loading <= '0';
			rx_data <= "00000000";
		else
			if (rx_reading = '0' and rx_in = '0') then
				rx_reading <= '1';
				rx_load <= '0';
				rx_loading <= '0';
				rx_delay <= 0;
				rx_prl_data <= "00000000";
			else
				if (rx_reading = '1' and rx_delay < 435) then
				rx_delay <= rx_delay +1;
				else
					if (rx_reading = '1' and rx_count < 8) then
						rx_prl_data <= rx_in & rx_prl_data (7 downto 1);
						rx_count <= rx_count + 1;
						rx_delay <= 0;
					else
						if (rx_reading = '1' and rx_count = 8 and rx_in = '1') then
							rx_delay <= 10;
							rx_count <= rx_count + 1;
						else
							if (rx_reading = '1' and rx_count = 8 and rx_in = '0') then
								rx_prl_data <= "00000000";
								rx_delay <= 0;
								rx_count <= 0;
								rx_reading <= '0';
								rx_load <= '0';
							else
								if (rx_reading = '1' and rx_count = 9 and rx_loading = '0') then
									
									rx_load <= '1';
									rx_loading <= '1';
									rx_data <= rx_prl_data;
								else
									rx_load <= '0';
									rx_loading <= '0';
									rx_count <= 0;
									rx_delay <= 0;
									rx_reading <= '0';
									rx_data <= "00000000";
								end if;
							end if;
						end if;
					end if;
				end if;
			end if;
		end if;
	end if;
	end process;
	
	process (clk, reset)
	begin
	if (clk = '1' and clk'event) then
		if (reset = '0') then
			tx_out <= '1';
			tx_delay <= 0;
			tx_count <= 0;
			tx_sending <= '0';
		else
			if (tx_send = '0' and tx_sending = '0') then
				tx_out <= '0';
				tx_delay <= 0;
				tx_count <= 0;
				tx_sending <= '1';
				tx_prl_data <= tx_data;
			else
				if (tx_sending = '1' and tx_delay < 434) then
					tx_delay <= tx_delay +1;
				else
					if (tx_sending = '1' and tx_count < 8) then
						tx_out <= tx_prl_data(tx_count);
						tx_count <= tx_count +1;
						tx_delay <= 0;
					else
						tx_out <= '1';
						if (tx_delay = 434) then
							if (tx_send = '1') then
								tx_sending <= '0';
								tx_delay <= 0;
								tx_count <= 0;
							end if;
						end if;
					end if;
				end if;
			end if;
		end if;
	end if;
	end process;
end rtl;

---------- UART Register ----------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity My_UARTRegister is

	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector (7 downto 0);
			data_out1	: OUT std_logic_vector (7 downto 0);
			data_out2	: OUT std_logic_vector (7 downto 0);
			data_out3	: OUT std_logic_vector (7 downto 0);
			data_out4	: OUT std_logic_vector (7 downto 0);
			data_frame	: out std_logic;
			data_sao	: out std_logic;
			data_bpm	: out std_logic;
			data_graph	: out std_logic;
			data_ready	: out std_logic;
			data_stored	: in std_logic
			);
end My_UARTRegister;

ARCHITECTURE behav OF My_UARTRegister IS
SIGNAL d1, d2, d3, d4 : std_logic_vector (7 downto 0);
SIGNAL count : integer;
SIGNAL sao, bpm, graph, frame: std_logic;
BEGIN
PROCESS(clk, reset, load, data_in, data_stored) 
	BEGIN
	if (clk'event and clk='1') then
		if (reset = '0') then
			data_out1 <= "00000000";
			data_out2 <= "00000000";
			data_out3 <= "00000000";
			data_out4 <= "00000000";
			data_frame <= '0';
			data_sao <= '0';
			data_bpm <= '0';
			data_graph <= '0';
			frame <= '0';
			sao <= '0';
			bpm <= '0';
			graph <= '0';
			count <= 0;
			data_ready <= '0';
		else
			if (count = 0 and load = '1') then
				count <= count +1;
				frame <= data_in(0);
				sao <= data_in(1);
				bpm <= data_in(2);
				graph <= data_in(3);
			else
				if (count = 1 and load = '1') then
					d1 <= data_in;
					count <= count +1;
				else
					if (count = 2 and load = '1') then
						d2 <= data_in;
						count <= count +1;
					else
						if (count = 3 and load = '1') then
							d3 <= data_in;
							count <= count +1;
						else
							if (count = 4 and load = '1') then
								d4 <= data_in;
								count <= count +1;
							else
								if (count = 5) then
									data_frame <= frame;
									data_sao <= sao;
									data_bpm <= bpm;
									data_graph <= graph;
									data_ready <= '1';
									count <= count +1;
									data_out1 <= d1;
									data_out2 <= d2;
									data_out3 <= d3;
									data_out4 <= d4;
								else
									if (count = 6 and data_stored = '1') then
										data_out1 <= "00000000";
										data_out2 <= "00000000";
										data_out3 <= "00000000";
										data_out4 <= "00000000";
										data_frame <= '0';
										data_sao <= '0';
										data_bpm <= '0';
										data_graph <= '0';
										data_ready <= '0';
										frame <= '0';
										sao <= '0';
										bpm <= '0';
										graph <= '0';
										count <= 0;
									end if;
								end if;
							end if;
						end if;
					end if;
				end if;
			end if;
		end if;
	end if;
	END PROCESS;
END behav;
---------Top level--------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity toplevel is
	port(	CLOCK_50	: in std_logic;
--			SW			: in STD_logic_vector (17 downto 0);
			SRAM_ADDR	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
			SRAM_WE_N	: OUT STD_LOGIC;
			SRAM_OE_N	: OUT STD_LOGIC;
			SRAM_CE_N	: OUT STD_LOGIC;
			SRAM_UB_N	: OUT STD_LOGIC;
			SRAM_LB_N	: OUT STD_LOGIC;
			SRAM_DQ		: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			GPIO_0		: inout STD_logic_vector (35 downto 0);
			KEY			: in STD_logic_vector (3 downto 0);
			UART_RXD	: IN STD_LOGIC;
			UART_TXD	: OUT STD_LOGIC
			);
end toplevel;

Architecture struct of toplevel is

component Dinclk is
	port(	clk			: in std_logic;
			reset		: in std_logic;
			iyin 		: in std_logic_vector(7 downto 0);
			idin		: in std_logic_vector (11 downto 0);
			id			: out std_logic;
			idr			: out std_logic;
			clkout		: out std_logic
			);
END component;

component XYclk is
	port(	clk			: in std_logic;
			reset		: in std_logic;
			ixin		: in std_logic_vector(7 downto 0);
			ix			: out std_logic;
			ixr			: out std_logic;
			iyin		: in std_logic_vector(7 downto 0);
			iy			: out std_logic;
			iyr			: out std_logic;
			clkout		: out std_logic_vector (1 downto 0)
			);
end component;

component My_dff is
	port(	clk			: in std_logic;
			data_in		: in std_logic_vector (2 downto 0);
			data_out	: out std_logic_vector (2 downto 0)
		);
end component;

component My_8bdff is
	port(	clk			: in std_logic;
			data_in		: in std_logic_vector (7 downto 0);
			data_out	: out std_logic_vector (7 downto 0)
		);
end component;

component My_8clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			reset  		: in std_logic
			);
end component;

component My_16clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			reset  		: in std_logic
			);
end component;

component My_6bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (5 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END component;  

component My_8bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (7 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END component;

component My_9bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (8 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END component;

component My_12bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (11 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END component;

component My_16index IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (15 downto 0);
			counterR	: OUT std_logic_vector (15 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END component; 

component My_18bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
end component;

component My_18bCounter40 IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
end component;  

component My_18bCounter40_0 IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
end component;  

component My_printsceern is
	port(
			clk			: in std_logic;
			reset		: in STD_logic;
			data_inU	: in STD_logic_vector (15 downto 0);
			data_inL	: in STD_logic_vector (15 downto 0);
			GPIO_0		: inout STD_logic_vector (7 downto 0)
			);
end component;

component My_sramctrl is
	port(
			clk			: in std_logic;
			reset		: in STD_logic;
			dinin		: in STD_logic_vector (11 downto 0);
			
			SRAM_ADDR 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
			SRAM_WE_N 	: OUT STD_LOGIC;
			SRAM_OE_N 	: OUT STD_LOGIC;
			SRAM_CE_N 	: OUT STD_LOGIC;
			SRAM_UB_N 	: OUT STD_LOGIC;
			SRAM_LB_N 	: OUT STD_LOGIC;
			SRAM_DQ 	: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			
			adcounter	: in std_logic_vector (17 downto 0);
			adcount 	: out std_logic;
			adreset		: out std_logic;
			
			dlycounter	: in std_logic_vector (5 downto 0);
			dlycount 	: out std_logic;
			dlyreset	: out std_logic;
			
			frmcounter	: in std_logic_vector (17 downto 0);
			frmcount 	: out std_logic;
			frmreset	: out std_logic;
			
			numcounter	: in std_logic_vector (17 downto 0);
			numcount	: out std_logic;
			numreset	: out std_logic;
			
			saocounter	: in std_logic_vector (17 downto 0);
			saocount	: out std_logic;
			saoreset	: out std_logic;
			
			graphcounter: in std_logic_vector (17 downto 0);
			graphcount	: out std_logic;
			graphreset	: out std_logic;
			
			fillcounter	: in std_logic_vector (17 downto 0);
			fillcount	: out std_logic;
			fillreset	: out std_logic;
			
			indxcounter	: in std_logic_vector (15 downto 0);
			indxcounterR: in std_logic_vector (15 downto 0);
			indxcount	: out std_logic;
			indxreset	: out std_logic;
			
			Ur_reset 	: OUT std_logic;
			Ur_load 	: OUT std_logic;
			Ur_data_in	: OUT std_logic_vector (15 downto 0);
			Lr_reset 	: OUT std_logic;
			Lr_load 	: OUT std_logic;
			Lr_data_in	: OUT std_logic_vector (15 downto 0);
			
			numr_reset 	: OUT std_logic;
			numr_load 	: OUT std_logic;
			numr_data_in: OUT std_logic_vector (15 downto 0);
			numr_data_out: IN std_logic_vector (15 downto 0);
			
			delr_reset 	: OUT std_logic;
			delr_load 	: OUT std_logic;
			delr_data_in: OUT std_logic_vector (15 downto 0);
			delr_data_out: IN std_logic_vector (15 downto 0);
			
			adr_reset 	: OUT std_logic;
			adr_load 	: OUT std_logic;
			adr_data_in: OUT std_logic_vector (17 downto 0);
			adr_data_out: IN std_logic_vector (17 downto 0);
			adr_data_out2: IN std_logic_vector (17 downto 0);
			adr_data_out3: IN std_logic_vector (17 downto 0);
			
			data_in1	: in std_logic_vector (7 downto 0);
			data_in2	: in std_logic_vector (7 downto 0);
			data_in3	: in std_logic_vector (7 downto 0);
			data_in4	: in std_logic_vector (7 downto 0);
			data_frame	: in std_logic;
			data_sao	: in std_logic;
			data_bpm	: in std_logic;
			data_graph	: in std_logic;
			data_ready	: in std_logic;
			data_stored	: out std_logic;
			
			flag_reset: OUT std_logic;
			flag_on	: OUT std_logic;
			flag_in	: IN std_logic
			);
end component;

component My_16bRegister IS
	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector ( 15 downto 0);
			data_out	: OUT std_logic_vector (15 downto 0)
			);
END component;

component My_addRegister is

	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector (17 downto 0);
			data_out	: OUT std_logic_vector (17 downto 0);
			data_out2	: OUT std_logic_vector (17 downto 0);
			data_out3	: OUT std_logic_vector (17 downto 0)
			);
end component;

component My_UARTRegister is

	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector (7 downto 0);
			data_out1	: OUT std_logic_vector (7 downto 0);
			data_out2	: OUT std_logic_vector (7 downto 0);
			data_out3	: OUT std_logic_vector (7 downto 0);
			data_out4	: OUT std_logic_vector (7 downto 0);
			data_frame	: out std_logic;
			data_sao	: out std_logic;
			data_bpm	: out std_logic;
			data_graph	: out std_logic;
			data_ready	: out std_logic;
			data_stored	: in std_logic
			);
end component;

component uart is
	port(	clk			: in std_logic;
			reset		: in std_logic;
			rx_data		: out std_logic_vector (7 downto 0);
			rx_in		: in std_logic;
			rx_load		: out std_logic;

			tx_data		: in std_logic_vector (7 downto 0);
			tx_out		: out  std_logic;
			tx_send		: in std_logic
			);
end component;

component My_flag is
	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			flag_out	: OUT std_logic
			);
end component;

SIGNAL clk8, clk16, clk82, clk162, resetdly, countdly, resetx, countx, resety, county, resetdin, countdin, adcount, adreset, frmcount, frmreset,
		numcount, numreset, saocount, saoreset, indxcount, indxreset, graphcount, graphreset, fillcount, fillreset,
		flag_reset, flag_on, flag_out,
		Din_clk, UR_reset, UR_load, LR_reset, LR_load, rx_load_reg, numR_reset, numR_load, delR_reset, delR_load, adR_reset, adR_load,
		tx_busy, tx_send, reg_data_frame, sram_data_stored, store_frame,
		store_graph, store_sao, store_bpm, store_data: std_logic;
SIGNAL XY_clk 					: std_logic_vector (1 downto 0);
SIGNAL XYD_in, XYD_out 			: std_logic_vector (2 downto 0);
SIGNAL dlyval					: std_logic_vector (5 downto 0);
SIGNAL xval, yval, datadff, dataout, rx_data_reg, reg_data_sram, tx_data, uart_d1, uart_d2, uart_d3, uart_d4		: std_logic_vector(7 downto 0);
--SIGNAL fillcounter : std_logic_vector(8 downto 0);
SIGNAL dinval					: std_logic_vector(11 downto 0);
SIGNAL UR_data_in, UR_data_out, LR_data_in, LR_data_out, numR_data_in, numR_data_out, delR_data_in, delR_data_out, indxcounter, indxcounterR: std_logic_vector(15 downto 0);
SIGNAL adcounter, frmcounter, numcounter, saocounter, graphcounter, adR_data_in, adR_data_out, adR_data_out2, adR_data_out3, fillcounter: std_logic_vector(17 downto 0);

begin
	clkdiv_8	: My_8clkdiv		port map (CLOCK_50, clk8, KEY(0));
--	clkdiv_16	: My_16clkdiv		port map (CLOCK_50, clk16, KEY(0));
--	clkdiv_82	: My_8clkdiv		port map (CLOCK_50, clk82, KEY(0));
--	clkdiv_162	: My_16clkdiv		port map (CLOCK_50, clk162, KEY(0));
	XY_1		: XYclk				port map (clk8, KEY(0), xval, countx, resetx, yval, county, resety, XY_clk);
	Din			: Dinclk			port map (CLOCK_50, KEY(0), yval, dinval, countdin, resetdin, Din_clk);
	delaycount	: My_6bCounter		port map (CLOCK_50, dlyval, countdly, resetdly);
	xcount		: My_8bCounter		port map (clk8, xval, countx, resetx);
	ycount		: My_8bCounter		port map (clk8, yval, county, resety);
	dincount	: My_12bCounter		port map (CLOCK_50, dinval, countdin, resetdin);
	indx_counter: My_16index		port map (CLOCK_50, indxcounter, indxcounterR, indxcount, indxreset);
	add_counter	: My_18bCounter		port map (CLOCK_50, adcounter, adcount, adreset);
	frm_counter	: My_18bCounter		port map (CLOCK_50, frmcounter, frmcount, frmreset);
	num_counter	: My_18bCounter		port map (CLOCK_50, numcounter, numcount, numreset);
	grph_counter: My_18bCounter		port map (CLOCK_50, graphcounter, graphcount, graphreset);
	sao_counter	: My_18bCounter40	port map (CLOCK_50, saocounter, saocount, saoreset);
	fill_counter: My_18bCounter40_0	port map (CLOCK_50, fillcounter, fillcount, fillreset);
	gfilter		: My_dff			port map (CLOCK_50, XYD_in, XYD_out);
	upper_reg	: My_16bregister	port map (CLOCK_50, UR_reset, UR_load, UR_data_in, UR_data_out);
	lower_reg	: My_16bregister	port map (CLOCK_50, LR_reset, LR_load, LR_data_in, LR_data_out);
--	data_dff	: My_8bdff			port map (clk8, datadff, dataout);
	number_reg	: My_16bregister	port map (CLOCK_50, numR_reset, numR_load, numR_data_in, numR_data_out);
	del_reg		: My_16bregister	port map (CLOCK_50, delR_reset, delR_load, delR_data_in, delR_data_out);
	address_reg	: My_addRegister	port map (CLOCK_50, adR_reset, adR_load, adR_data_in, adR_data_out, adR_data_out2, adR_data_out3);
	pscreen		: My_printsceern	port map (CLOCK_50, KEY(0), UR_data_out, LR_data_out, dataout);
	saoflag		: My_flag			port map (CLOCK_50, flag_reset, flag_on, flag_out);
	sramcontrol	: My_sramctrl		port map (CLOCK_50, KEY(0), dinval, SRAM_ADDR, SRAM_WE_N, SRAM_OE_N, SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_DQ, 
												adcounter, adcount, adreset, dlyval, countdly, resetdly, frmcounter, frmcount, frmreset,
												numcounter, numcount, numreset, saocounter, saocount, saoreset,
												graphcounter, graphcount, graphreset, fillcounter, fillcount, fillreset,
												indxcounter, indxcounterR, indxcount, indxreset,
												UR_reset, UR_load, UR_data_in, LR_reset, LR_load, LR_data_in, 
												numR_reset, numR_load, numR_data_in, numR_data_out, delR_reset, delR_load, delR_data_in, delR_data_out,
												adR_reset, adR_load, adR_data_in, adR_data_out, adR_data_out2, adR_data_out3,
												uart_d1, uart_d2, uart_d3, uart_d4, store_frame, store_sao, store_bpm, store_graph, store_data, sram_data_stored,
												flag_reset, flag_on, flag_out);

	uartmodule	: UART				port map (CLOCK_50, KEY(0), rx_data_reg, UART_RXD, rx_load_reg, tx_data, UART_TXD, KEY(1));
	uartregister: My_UARTRegister	port map (CLOCK_50, KEY(0), rx_load_reg, rx_data_reg, uart_d1, uart_d2, uart_d3, uart_d4, 
											store_frame, store_sao, store_bpm, store_graph, store_data, sram_data_stored);
	
	XYD_in(1 downto 0) <= XY_clk;
	XYD_in(2) <= Din_clk;
	
	GPIO_0 (13)	<= '0';

	GPIO_0 (15)	<= XYD_out(0);
	GPIO_0 (19)	<= XYD_out(1);
	GPIO_0 (17)	<= XYD_out(2);
	GPIO_0 (21) <= dataout(3);
	GPIO_0 (23) <= dataout(2);
	GPIO_0 (25) <= dataout(1);
	GPIO_0 (27) <= dataout(0);
	GPIO_0 (29) <= dataout(7);
	GPIO_0 (31) <= dataout(6);
	GPIO_0 (33) <= dataout(5);
	GPIO_0 (35) <= dataout(4);
	
	tx_data <= "10101111";
End struct;
